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data sheet march 1999 quad differential receivers BRF1A, brf2a, brr1a, brs2a, and brt1a features n pin equivalent to the general-trade 26ls32 device, with improved speed, reduced power consumption, and significantly lower levels of emi n high input impedance @ 8 k w n four line receivers per package n 400 mbits/s maximum data rate when used with lucent technologies microelectronics group data transmission drivers n meets esdi standards n 4.0 ns maximum propagation delay n <0.20 v input sensitivity n - 1.2 v to + 7.2 v common-mode range n - 40 c to + 125 c ambient operating temperature range (wider than the 41 series) n single 5.0 v 10% supply n output defaults to logic 1 when inputs are left open* n available in four package types n lower power requirement than the 41 series description these quad differential receivers accept digital data over balanced transmission lines. they translate dif- ferential input logic levels to ttl output logic levels. all devices in this family have four receivers with a common enable control. these receivers are pin equivalent to the general-trade 26ls32, but offer increased speed and decreased power consumption. they replace the lucent 41 series receivers. * this feature is available on BRF1A and brf2a. the BRF1A device is the generic receiver in this fam- ily and requires the user to supply external resistors on the circuit board for impedance matching. the brf2a is identical to the BRF1A but has an esd protection circuit added to significantly improve the esd (hbm) characteristics on the differential input terminals. the brs2a is identical to the brf2a but has a pre- ferred state feature that places the output in the high state when the inputs are open, shorted to ground, or shorted to the power supply. the brr1a is equivalent to the BRF1A, but has a 110 w resistor connected across the differential inputs. this eliminates the need for an external resis- tor when terminating a 100 w impedance line. this device is designed to work with the bdp1a or bpnpa in point-to-point applications. the brt1a is equivalent to the BRF1A; however, it is provided with a y-type resistor network across the dif- ferential inputs and terminated to ground. the y-type termination provides the best emi results. this device is not recommended for applications where the differences in ground voltage between the driver and the receiver exceed 1 v. this device is designed to work with the bdg1a or bpnga in point-to-point applications. the powerdown loading characteristics of the receiver input circuit are approximately 8 k w relative to the power supplies; hence, they will not load the transmission line when the circuit is powered down. for those circuits with termination resistors, the line will remain impedance matched when the circuit is powered down. the packaging options that are available for these quad differential line drivers include a 16-pin dip; a 16-pin, j-lead soj; a 16-pin, gull-wing soic; and a 16-pin, narrow-body, gull-wing soic.
2 lucent technologies inc. data sheet march 1999 BRF1A, brf2a, brr1a, brs2a, and brt1a quad differential receivers pin information 12-2281ac figure 1. quad differential receiver logic diagrams table 1. enable truth table absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. electrical characteristics for electrical characteristics over the temperature range, see figures 7 through 10. table 2. power supply current characteristics see figure 7 for variation in i cc over the temperature range. t a = C40 c to +125 c, v cc = 5 v 0.5 v. e1 e2 condition 00active 10active 01disabled 11active parameter symbol min max unit power supply voltage v cc 6.5 v ambient operating temperature t a - 40 125 c storage temperature t stg - 55 150 c parameter symbol min typ max unit power supply current (v cc = 5.5 v): all outputs disabled i cc ? 30 45 ma all outputs enabled i cc ? 20 32 ma 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 e1 16 15 14 13 12 11 10 9 ai ai ao bo bi bi gnd do v cc di di e2 co ci ci e1 ai ai ao bo bi bi gnd do v cc di di e2 co ci ci a d b c a d b c brr1a brt1a 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 e1 ai ai ao bo bi bi gnd do v cc di di e2 co ci ci a d b c BRF1A brf2a
lucent technologies inc. 3 data sheet march 1999 BRF1A, brf2a, brr1a, brs2a, and brt1a quad differential receivers electrical characteristics (continued) table 3. voltage and current characteristics for variation in minimum v oh and maximum v ol over the temperature range, see figure 8. t a = C40 c to +125 c. * the input levels and difference voltage provide zero noise immunity and should be tested only in a static, noise-free environm ent. ? outputs of unused receivers assume a logic 1 level when the inputs are left open. (it is recommended that all unused positive inputs be tied to the positive power supply. no external series resistor is required.) ? test must be performed one lead at a time to prevent damage to the device. see figure 2. 12-2819af figure 2. brt1a terminating resistor configuration parameter sym min typ max unit output voltages, v cc = 4.5 v: low, i ol = 8.0 ma v ol 0.5v high, i oh = - 400 m av oh 2.4 v enable input voltages: low, v cc = 5.5 v v il * 0.7 v high, v cc = 5.5 v v ih *2.0 v clamp, v cc = 4.5 v, i i = C5.0 ma v ik C1.0 differential input voltages, v ih C v il : ? - 0.80 v < v ih < 7.2 v, - 1.2 v < v il < 6.8 v v th * 0.1 0.20 v input offset voltage v off ? 0.02 0.05 v input offset voltage brs2a v off ? 0.1 0.15 v output currents, v cc = 5.5 v: off-state (high z), v o = 0.4 v i ozl C20a off-state (high z), v o = 2.4 v i ozh 20a short circuit i os ? C25 C100 ma enable currents, v cc = 5.5 v: low, v in = 0.4 v i il C400 a high, v in = 2.7 v i ih 20a reverse, v in = 5.5 v i ih 100a differential input currents, v cc = 5.5 v: low, v in = C1.2 v i il - 1.0 ma high, v in = 7.2 v i ih 1.0ma differential input impedance (brr1a): connected between ri and ri r o 110 w differential input impedance (brt1a) r 1 60 w r 2 90 w ri r1 r1 r2 ri
4 lucent technologies inc. data sheet march 1999 BRF1A, brf2a, brr1a, brs2a, and brt1a quad differential receivers timing characteristics table 4. timing characteristics (see figures 4 and 5.) for propagation delays (t plh and t phl ) over the temperature range, see figures 9 and 10. propagation delay test circuit connected to output is shown in figure 6. t a = C40 c to +125 c, v cc = 5 v 0.5 v. 12-3462f note: this graph is included as an aid to the system designers. total circuit delay varies with load capacitance. the total dela y is the sum of the delay due to the external capacitance and the intrinsic delay of the device. figure 3. typical extrinsic propagation delay versus load capacitance at 25 c parameter symbol min typ max unit propagation delay: input to output high t plh 1.5 2.5 4.0 ns input to output low t phl 1.5 2.5 4.0 ns disable time, c l = 5 pf: high-to-high impedance t phz 512ns low-to-high impedance t plz 512ns pulse width distortion, ltphl - tplhi: load capacitance (c l ) = 15 pf tskew1 0.7 ns load capacitance (c l ) = 150 pf tskew1 4.0 ns output waveform skews: part-to-part skew, t a = 75 c d tskew1p-p 0.8 1.4 ns part-to-part skew, t a = C40 c to +125 c d tskew1p-p 1.5 ns same part skew d tskew 0.3 ns enable time: high impedance to high t pzh 812ns high impedance to low t pzl 812ns rise time (20%80%) t tlh 3.0ns fall time (80%20%) t thl 3.0ns 25 50 75 100 125 150 0 load capacitance, c l (pf) 2 1 3 7 175 200 0 4 5 6 extrinsic propagation delay, t p (ns) t phl (typ) t plh (typ)
lucent technologies inc. 5 data sheet march 1999 BRF1A, brf2a, brr1a, brs2a, and brt1a quad differential receivers timing characteristics (continued) 12-2251af figure 4. receiver propagation delay timing 12-2538af * e2 = 1 while e1 changes state. ? e1 = 0 while e2 changes state. figure 5. receiver enable and disable timing test conditions parametric values specified under the electrical characteristics and timing characteristics sections for the data transmission driver devices are measured with the following output load circuits> 12-2249f *includes probe and jig capacitances. note: all 458e, in4148, or equivalent diodes. figure 6. receiver propagation delay test circuit input output input 80% 20% 3.7 v 3.2 v 2.7 v v oh 1.3 v v ol 80% 20% t phl t thl t plh t tlh d v = 0.5 v d v = 0.5 v d v = 0.5 v d v = 0.5 v e1* output t phz t pzh 3 v 1.3 v 0 v e2 ? 3 v 1.3 v 0 v v oh v ol 1.3 v t pzl t plz to output of device under test c l 15 pf* 5 k w 2 k w +5 v
6 lucent technologies inc. data sheet march 1999 BRF1A, brf2a, brr1a, brs2a, and brt1a quad differential receivers temperature characteristics 12-3463af figure 7. typical and maximum i cc versus temperature 12-3464af figure 8. minimum v oh and maximum v ol versus temperature at v cc = 4.5 v 12-3465c figure 9. propagation delay for a high output (t plh ) versus temperature at v cc = 5.0 v 12-3466c figure 10. propagation delay for a low output (t phl ) versus temperature at v cc = 5.0 v C25 0 25 50 75 100 18 26 temperature ( c) 22 20 24 32 125 150 28 i cc (ma) C50 30 i cc max v cc = 5.5 i cc typ v cc = 5.0 C25 0 25 50 75 100 0.0 1.6 temperature ( c) 0.8 0.4 1.2 2.8 125 150 2.0 voltage (v) C50 2.4 i oh min i ol max 3.2 3.6 3.8 C25 0 25 50 75 100 1.00 3.00 temperature ( c) 2.00 1.50 2.50 4.00 125 150 3.50 max typ min pr o pa g ati o n delay ( ns ) C50 C250 255075 1.00 1.50 2.00 4.00 125 150 C50 2.50 3.00 3.50 max typ min propagation delay (ns) temperature ( c) 100 handling precautions caution : this device is susceptible to damage as a result of electrostatic discharge. take proper precautions during both handling and testing. follow guidelines such as jedec publication no. 108-a (dec. 1988). when handling and mounting line driver products, proper precautions should be taken to avoid exposure to electrostatic discharge (esd). the user should adhere to the following basic rules for esd control: 1. assume that all electronic components are sensitive to esd damage. 2. never touch a sensitive component unless properly grounded. 3. never transport, store, or handle sensitive components except in a static-safe environment.
lucent technologies inc. 7 data sheet march 1999 BRF1A, brf2a, brr1a, brs2a, and brt1a quad differential receivers esd failure models lucent employs two models for esd events that can cause device damage or failure. 1. a human-body model (hbm) that is used by most of the industry for esd-susceptibility testing and pro- tection-design evaluation. esd voltage thresholds are dependent on the critical parameters used to define the model. a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes. 2. a charged-device model (cdm), which many believe is the better simulator of electronics manufacturing exposure. tables 5 and 6 illustrates the role these two models play in the overall prevention of esd damage. hbm esd testing is intended to simulate an esd event from a charged person. the cdm esd testing simulates charging and discharging events that occur in produc- tion equipment and processes, e.g., an integrated cir- cuit sliding down a shipping tube. the hbm esd threshold voltage presented here was obtained by using these circuit parameters. table 5. typical esd thresholds for data transmission receivers table 6. esd damage protection device hbm threshold cdm threshold differential inputs others BRF1A, brr1a, brt1a > 800 > 2000 > 1000 brf2a, brs2a > 2000 > 2000 > 2000 esd threat controls personnel processes control wrist straps esd shoes antistatic flooring static-dissipative materials air ionization model human-body model (hbm) charged-device model (cdm) latch-up latch-up evaluation has been performed on the data transmission receivers. latch-up testing determines if power- supply current exceeds the specified maximum due to the application of a stress to the device under test. a device is considered susceptible to latch-up if the power supply current exceeds the maximum level and remains at that level after the stress is removed. lucent performs latch-up testing per an internal test method that is consistent with jedec standard no. 17 (previ- ously jc-40.2) cmos latch-up standardized test procedure. latch-up evaluation involves three separate stresses to evaluate latch-up susceptibility levels: 1. dc current stressing of input and output pins. 2. power supply slew rate. 3. power supply overvoltage. table 7. latch-up test criteria and test results based on the results in table 7, the data transmission receivers pass the lucent latch-up testing requirements and are considered not susceptible to latch-up. dc current stress of i/o pins power supply slew rate power supply overvoltage data transmission receiver ics minimum criteria 3 150 ma 1 s 3 1.75 x vmax test results 3 250 ma 100 ns 3 2.25 x vmax
8 lucent technologies inc. data sheet march 1999 BRF1A, brf2a, brr1a, brs2a, and brt1a quad differential receivers outline diagrams 16-pin dip dimensions are in millimeters. 5-4410r.2 (c) note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schematics to assist you r design efforts, please contact your lucent technologies sales representative. package description number of pins (n) package dimensions maximum length (l) maximum width without leads (b) maximum width including leads (w) maximum height above board (h) pdip3 (plastic dual-in-line package) 16 20.57 6.48 7.87 5.08 w h 0.58 max 2.54 typ 0.38 min seating plane n 1 pin #1 identifier zone l b
lucent technologies inc. 9 data sheet march 1999 BRF1A, brf2a, brr1a, brs2a, and brt1a quad differential receivers outline diagrams (continued) 16-pin soic (sonb/sog) dimensions are in millimeters. 5-4414r.3 (c) note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schematics to assist you r design efforts, please contact your lucent technologies sales representative. package description number of pins (n) package dimensions maximum length (l) maximum width without leads (b) maximum width including leads (w) maximum height above board (h) sonb (small- outline, narrow body) 16 10.11 4.01 6.17 1.73 sog (small- outline, gull- wing) 16 10.49 7.62 10.64 2.67 w 0.61 0.51 max h 0.28 max 0.10 seating plane 1.27 typ n l b 1 pin #1 identifier zone
10 lucent technologies inc. data sheet march 1999 BRF1A, brf2a, brr1a, brs2a, and brt1a quad differential receivers outline diagrams (continued) 16-pin soic (soj) dimensions are in millimeters. 5-4413r.3 (c) note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schematics to assist you r design efforts, please contact your lucent technologies sales representative. package description number of pins (n) package dimensions maximum length (l) maximum width without leads (b) maximum width including leads (w) maximum height above board (h) soj (small- outline, j-lead) 16 10.41 7.62 8.81 3.18 n 1 pin #1 identifier zone 0.51 max 0.79 max 0.10 seating plane 1.27 typ h w b l
lucent technologies inc. 11 data sheet march 1999 BRF1A, brf2a, brr1a, brs2a, and brt1a quad differential receivers power dissipation system designers incorporating lucent data transmis- sion drivers in their applications should be aware of package and thermal information associated with these components. proper thermal management is essential to the long- term reliability of any plastic encapsulated integrated circuit. thermal management is especially important for surface-mount devices, given the increasing circuit pack density and resulting higher thermal density. a key aspect of thermal management involves the junc- tion temperature (silicon temperature) of the integrated circuit. several factors contribute to the resulting junction tem- perature of an integrated circuit: n ambient use temperature n device power dissipation n component placement on the board n thermal properties of the board n thermal impedance of the package thermal impedance of the package is referred to as q ja and is measured in c rise in junction temperature per watt of power dissipation. thermal impedance is also a function of airflow present in system application. the following equation can be used to estimate the junction temperature of any device: t j = t a + p d q ja where: t j is device junction temperature (c). t a is ambient temperature (c). p d is power dissipation (w). q ja is package thermal impedance (junction to ambient c/w). the power dissipation estimate is derived from two fac- tors: n internal device power n power associated with output terminations multiplying i cc times v cc provides an estimate of inter- nal power dissipation. the power dissipated in the output is a function of the: n termination scheme on the outputs n termination resistors n duty cycle of the output package thermal impedance depends on: n airflow n package type (e.g., dip, soic, soic/nb) the junction temperature can be calculated using the previous equation, after power dissipation levels and package thermal impedances are known. figure 11 illustrates the thermal impedance estimates for the various package types as a function of airflow. this figure shows that package thermal impedance is higher for the narrow-body soic package. particular attention should, therefore, be paid to the thermal man- agement issues when using this package type. in general, system designers should attempt to main- tain junction temperature below 125 c. the following factors should be used to determine if specific data transmission drivers in particular package types meet the system reliability objectives: n system ambient temperature n power dissipation n package type n airflow 12-2753f figure 11. power dissipation dip soic/nb j-lead soic/gull wing airflow (ft./min.) 200 400 600 800 1000 1200 0 40 50 60 70 80 90 100 110 120 130 140 thermal resistance q ja ( c/w)
d a t a s h e et ma r ch 1999 BRF1A, brf2a, brr1a, brs2a, and b r t1a quad dif f erent i al rece i ve r s l u cent t echn o logies i n c. re s e r v es t h e r i g ht t o ma k e chan g es to t he p r oduct ( s) o r in f o r m ation c o ntain e d he r ein with o ut no t i c e . n o liability i s assum e d as a res u l t of t h eir us e or applicatio n . no rights u nde r a n y pa t ent acc o mpa n y the s a l e of a n y such p r oduct ( s) o r in f o r m a tion. co p yright ? 199 9 luce n t t ec h nologie s inc. all rights res e r v ed ma r ch 19 9 9 ds99-196hsi (replace s ds99-008hsi) f o r a d d i ti o n a l i n fo r m a t i o n , c o n ta c t y o u r m i c r o e l e c t r o n i c s g r o u p a cc o u n t m a n a ge r o r t h e f o l l o wi n g: i n terne t : http://ww w . lucent.com/mic r o e-m a il: do c m a ste r @mi c r o .lu c ent. c om n. a m erica : microelectronics grou p , lucent t echnologies i nc., 555 union boul e v ard, room 30l-15 p -ba, allent o wn , p a 18103 1 - 80 0 - 37 2 - 2 4 4 7 , f a x 6 10 -7 1 2 - 4 1 06 ( i n c an a d a: 1 - 8 0 0 - 5 5 3 - 2 44 8 , f a x 6 1 0 - 71 2 - 4 1 06) asia p a cif i c : microelectronics grou p , lucent t echnologies singapore pt e . l t d. , 77 s cience p a r k d r i v e , #03-18 cintech iii , singa p o r e 1 1 82 5 6 t el. ( 65 ) 7 7 8 8 8 33 , f a x ( 6 5 ) 7 7 7 74 9 5 c h i n a: m i c r o e l e c t r o n i cs g r o u p , l u c e n t t e c hn o l o g i e s ( c h i na ) c o ., lt d ., a- f2 , 2 3 / f , za o f o n g u n i v e r s e b u i l d i n g , 18 0 0 zho n g s h a n x i r o a d , s h a ng h a i 2 00 2 3 3 p . r. c h i na t el. ( 86 ) 21 64 4 0 0 4 6 8 , ext . 316 , f a x ( 86 ) 21 64 4 0 0 6 5 2 j a p a n: m i c r o e l e c t r o n i cs g r o u p , l u c e n t t e c h n o l og i e s j ap a n l t d ., 7 - 1 8 , h i ga s h i - g o ta n d a 2 -c h o m e , s h i n a g a w a - k u , t o k y o 1 4 1, j a p an t el. ( 81 ) 3 5 42 1 1 6 0 0 , f a x ( 8 1 ) 3 5 4 2 1 17 0 0 e u r o p e : d at a r e qu e s t s : m ic r o e l e c t r o n ic s g r ou p d a t a li n e : t e l. ( 4 4 ) 1 18 9 3 2 4 29 9 , f a x ( 4 4 ) 1 1 8 9 3 2 8 148 t e c h n i cal i n q u i r i e s : ge r ma n y : ( 4 9 ) 8 9 9 50 8 6 0 (m u n i c h ) , u n i t e d ki n gdo m : ( 4 4 ) 1 3 44 86 5 9 0 0 (ascot), f r a n ce : ( 3 3 ) 1 4 0 8 3 6 8 0 0 (p a r i s), s we d e n : ( 4 6) 8 5 9 4 6 07 00 (sto c k h o l m) , fi n land : ( 3 5 8 ) 9 4 3 54 28 0 0 (h e ls i n k i), i t a l y : ( 3 9 ) 0 2 6 6 0 8 13 1 (m i l a n), s p ai n : ( 3 4 ) 1 8 0 7 1 4 4 1 (mad r id) o r dering in f ormation p a r t n um b er p a c k a g e t y p e c o mc o d e f o r m e r pk g. t y pe f o r m e r p a r t # b r f 1 a 1 6 e 1 6 - pi n , p l a stic s oj 1 07 9 4 9 9 2 7 1 0 4 1 l f , m f , l s b r f 1 a 1 6e -t r t a p e & r e e l soj 1 07 9 4 9 9 3 5 1 0 41 l f , m f , ls b r f 1 a 1 6 g 1 6 - pi n , p l a stic s o i c 1 0 7 9 5 0 2 9 7 1 1 4 1 l f , m f , l s b r f 1 a 1 6g -t r t a p e & r e e l so i c 1 07 9 5 0 3 0 5 1 1 41 l f , m f , ls b r f 1 a 1 6 n b 1 6 - pi n , p l a stic s o i c / nb 1 07 9 4 9 9 6 8 1 2 4 1 l f , m f , l s b r f 1 a 1 6 n b- t r t a p e & r e e l s o i c /nb 1 0 7 9 4 9 9 7 6 1 2 4 1 l f , m f , l s b r f 1 a 1 6 p 1 6 - pi n , p l a stic d ip 1 07 9 4 9 9 8 4 4 1 l f , m f , l s b r f 2 a 1 6 e 1 6 - pi n , p l a stic s oj 1 07 9 4 9 9 9 2 1 0 4 1 l f 2, m f2 b r f 2 a 1 6e -t r t a p e & r e e l soj 1 07 9 5 0 0 0 8 1 0 41 l f 2 , m f 2 b r f 2 a 1 6 g 1 6 - pi n , p l a stic s o i c 1 0 7 9 5 0 0 1 6 1 1 4 1 l f 2, m f2 b r f 2 a 1 6g -t r t a p e & r e e l so i c 1 07 9 5 0 0 2 4 1 1 41 l f 2 , m f 2 b r f 2 a 1 6 n b 1 6 - pi n , p l a stic s o i c / nb 1 07 9 5 0 0 3 2 1 2 4 1 l f 2, m f2 b r f 2 a 1 6n b - t r t a p e & r e e l so i c /n b 1 07 9 5 0 0 4 0 1 2 41 l f 2 , m f 2 b r f 2 a 1 6 p 1 6 - pi n , p l a stic d ip 1 07 9 5 0 0 5 7 4 1 l f 2, m f2 b r r 1 a 1 6e 1 6 - pi n , p l a stic s oj 1 07 9 5 0 0 6 5 1 0 4 1 l r, m r b r r 1 a 1 6 e -tr t a p e & r e e l s o j 1 07 9 5 0 0 7 3 1 0 4 1 l r, m r b r r 1 a 1 6g 1 6 - pi n , p l a stic s o i c 1 0 7 9 5 0 0 8 1 1 1 4 1 l r, m r b r r 1 a 1 6 g - t r t a p e & r e e l s o ic 1 07 9 5 0 0 9 9 1 1 4 1 l r, m r b r r 1 a 1 6 n b 1 6 - pi n , p l a stic s o i c / nb 1 07 9 5 0 1 0 7 1 2 4 1 l r, m r b r r 1 a 1 6 n b - tr t a p e & r e e l s o i c /nb 1 0 7 9 5 0 1 1 5 1 2 4 1 l r, m r b r r 1 a 1 6p 1 6 - pi n , p l a stic d ip 1 07 9 5 0 1 2 3 4 1 l r, m r b r s 2 a 1 6e 1 6 - pi n , p l a stic s oj 1 08 2 4 4 7 3 2 1 0 4 1 m f , m f 2, ls b r s 2 a 1 6 e -tr t a p e & r e e l s o j 1 08 2 4 4 7 4 0 1 0 4 1 m f , m f 2, ls b r s 2 a 1 6g 1 6 - pi n , p l a stic s o i c 1 0 8 2 4 4 7 5 7 1 1 4 1 m f , m f 2, ls b r s 2 a 1 6 g - t r t a p e & r e e l s o ic 1 08 2 4 4 7 6 5 1 1 4 1 m f , m f 2, ls b r s 2 a 1 6p 1 6 - pi n , p l a stic d ip 1 08 2 4 4 7 9 9 4 1 m f , m f 2, ls b r s 2 a 1 6 n b 1 6 - pi n , p l a stic s o i c / nb 1 08 2 4 4 7 7 3 1 2 4 1 m f , m f 2, ls b r s 2 a 1 6 n b - tr t a p e & r e e l s o i c /nb 1 0 8 2 4 4 7 8 1 1 2 4 1 m f , m f 2, ls b r t 1 a 1 6e 1 6 - pi n , p l a stic s oj 1 07 9 5 0 1 3 1 1 0 4 1 l t , m t b r t 1 a 1 6 e - t r t a p e & r e e l s o j 1 07 9 5 0 1 4 9 1 0 4 1 l t , m t b r t 1 a 1 6g 1 6 - pi n , p l a stic s o i c 1 0 7 9 5 0 1 5 6 1 1 4 1 l t , m t b r t 1 a 1 6 g - t r t a p e & r e e l s o ic 1 07 9 5 0 1 6 4 1 1 4 1 l t , m t b r t 1 a 1 6 n b 1 6 - pi n , p l a stic s o i c / nb 1 07 9 5 0 3 1 3 1 2 4 1 l t , m t b r t 1 a 1 6 n b -tr t a p e & r e e l s o i c /nb 1 0 7 9 5 0 3 2 1 1 2 4 1 l t , m t b r t 1 a 1 6p 1 6 - pi n , p l a stic d ip 1 07 9 5 0 3 3 9 4 1 l t , m t

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